1. Field of the Invention
The present invention generally relates to a semiconductor process, and in particular, to a through substrate via (TSV) process.
2. Description of Related Art
Along with the rapid development in techniques of the semiconductor process, further improvement in integration and performance of the semiconductor device is demanded, which advances the development in the structure of stacking wafers. The TSV process is one of the common techniques for fabricating the stacked wafer structure. During the TSV process, holes with high aspect ratio are first formed in the substrate of the wafer, and are then filled with a conductive material. Subsequently, a chemical mechanical polishing (CMP) process is performed, so as to remove the conductive material disposed outside the holes. Afterwards, a portion of the substrate at the backside is removed, so as to thin the substrate and expose the conductive material disposed in the holes. Thereafter, a plurality of wafers is bonded together in a stacked manner, and the wafers electrically connect with one another via the conductive material deployed in the holes.
In general, the TSV can be classified into 4 types, however each type of the TSV process exists its respective defects.
The first type of the TSV process is performed before the fabrication of the semiconductor device, e.g. metal oxide semiconductor (MOS) transistor. When the conductive material filling the holes is metal, contamination usually occurs on the wafer which makes a great impact on the subsequent process, and the metal filling the holes cannot endure the high temperature during the fabrication of the semiconductor device to be formed, e.g. the high temperature of conducting a thermal oxidation process for forming a gate dielectric layer, and the high temperature of conducting a source/drain region activation process. In addition, if the holes are filled with polysilicon to prevent the contamination problem mentioned above, the performance of the device is affected due to high resistance of polysilicon.
The second type of the TSV process is performed after the fabrication of the semiconductor device, e.g. MOS transistor, and before the back-end-of-line (BEOL) process, e.g. interconnect process. Nevertheless, after the holes are filled with the conductive material, difficulty in the CMP process is raised because the semiconductor device has been formed on the substrate.
The third type of the TSV process is performed after the BEOL process and before the bonding of the wafers. However, the area of the wafer usually have to be increased, so as to keep sufficient space for the TSV process after the interconnect process. Besides, complexity of the interconnect process is often raised owing to reservation of the space for TSV process.
The forth type of the TSV process is performed after the bonding of the wafers. However, the bonding material utilized for bonding the wafers is usually damaged due to the incapability to bear the high temperature during the TSV process, so that the wafers cannot be bonded together.